module mcu_state_ack(
		input   wire            resetb,
        	input   wire            sclk,

		//和通讯模块接口
		input	wire		fpga_rec_flag,
		input	wire		fpga_send_flag,	
		input	wire		op_start_flag,
		input	wire	[31:0]	op_start_addr,
		input	wire	[7:0]	op_length,
		output	reg		op_ack,
		
		//反馈数据接口
		output	reg		fpga_send_end,
		output	reg		send_buf_we,
		output	wire	[7:0]	send_buf_waddr,
		output	wire	[7:0]	send_buf_wdata,
	        
		//通讯包接口
		input	wire	[15:0]	crc_error_sum,
		input	wire	[31:0]	pkt_sum,
		
		//级联序号
                input	wire		local_depth_en,
                input	wire	[7:0]   current_depth,

		//接口模块返回的状态数据
		input	wire	[7:0]	phy_state,
		
		//DMX模块返回的状态数据
		input	wire	[7:0]	dmx_state_data,
		
		//调试用返回的状态数据
		input	wire	[15:0]	debug_data,

		//输出给led灯和输出控制模块
		output 	wire	[7:0]	tout
		);

//******************************************************************/
//			   信号定义
//******************************************************************/		
//程序版本信息
parameter       main_function   =       8'h53;   //ASCII "S"
parameter       sub_function    =       8'h47;   //ASCII "G"
parameter       main_solution   =       8'd8;    //"8"       
parameter       sub_solution    =       8'd3;    //"03"
parameter       application_type=       8'h84;   //ASCII "T"
parameter       main_version    =       8'd7;    //"07"
parameter       sub_version     =       8'd47;   //X"47"       
parameter       mini_version	=       8'd01;   //_"1"       

reg		rec_flag_t;
reg	[2:0]	counter,counter_t,counter_tt;
reg		add_flag,add_flag_t,add_flag_tt;
reg		clr_flag,clr_flag_t;
reg		load_flag,load_flag_t;
reg	[8:0]	adder;
reg		cin;
reg		buf_wea;
reg	[3:0]	buf_waddr;
reg	[7:0]	buf_wdata;
reg	[3:0]	buf_raddr;
wire	[7:0]	buf_rdata;
reg     [7:0]   state_version;


reg	[7:0]	state_data;
wire	[7:0]	set_addr;
reg	[12:0]	set_count;
reg		state_active;
		
always @(posedge sclk)
	if (op_start_flag == 1 && fpga_send_flag == 1 && op_start_addr == 0)
		state_active <= 1;
	else if (set_count[12] == 1)
		state_active <= 0;
		
always @(posedge sclk)
	if (state_active == 1 && set_count < 16)
		op_ack <= 1;
	else
		op_ack <= 0;
		
always @(posedge sclk)
	if (state_active == 0)
		set_count <= 0;
	else if (set_count[12] == 0)
		set_count <= set_count + 1;

assign	set_addr = set_count[11:4];
	
always @(posedge sclk)
	if (state_active == 0)
		state_data <= 0;
	else if(set_addr[7:0] >=8'h80 && set_addr[7:0] <= 8'h9f)
		state_data <= dmx_state_data;
	else
		case(set_addr[7:0])
			'd0:state_data<=crc_error_sum[7:0];
			'd1:state_data<=crc_error_sum[15:8];
			'd2:state_data<=pkt_sum[7:0];
			'd3:state_data<=pkt_sum[15:8];
			'd4:state_data<=pkt_sum[23:16];
			'd5:state_data<=pkt_sum[31:24];
			'd6:state_data<=phy_state;
			'd7:state_data<=local_depth_en;
			'd8:state_data<=current_depth;
			'h30:state_data<=debug_data[7:0];
			'h31:state_data<=debug_data[15:8];
			'h40:state_data<=main_function;
			'h41:state_data<=sub_function;
			'h42:state_data<=main_solution;
			'h43:state_data<=sub_solution;
			'h44:state_data<=application_type;
			'h45:state_data<=main_version;
			'h46:state_data<=sub_version;
			'h47:state_data<=mini_version;
			'hFE:state_data<=8'hFE;
			'hFF:state_data<=8'hFF;
			default state_data<='d0;
		endcase

assign	send_buf_wdata = state_data;
assign	send_buf_waddr = set_addr;

always @(posedge sclk)
	if (set_count[3:0] == 10)
		send_buf_we <= 1;
	else
		send_buf_we <= 0;
	
always @(posedge sclk)
	if (set_count[12] == 1 && state_active == 1)
		fpga_send_end <= 1;
	else
		fpga_send_end <= 0;

endmodule